1. Field of the Invention
This invention is related to prefetch mechanisms in processors.
2. Description of the Related Art
Processors continue to be produced with both higher operating frequencies and higher average number of instructions executed per clock cycle (IPC). Memory latency, on the other hand, has only decreased at a much slower rate. Accordingly, processors are often stalled awaiting instructions and/or data from memory. In order to improve performance, processors typically include one or more levels of caching. Data stored in the cache may be available at a much lower latency than data from memory. Accordingly, cache hits may be provided with low latency and may improve performance of the processors. Cache misses are fetched from memory and incur the higher memory latencies.
In an attempt to reduce the effective memory latency even further, processors can implement prefetching. Generally, prefetching involves predicting which cache blocks the processor will need to access soon, and initiating the memory read for the cache blocks prior to such accesses being generated via instruction code execution in the processor. If the prefetching successfully reads cache blocks that are later accessed by the processor, memory latency is reduced because the accesses are cache hits instead of cache misses. On the other hand, inaccurate prefetching can cause useful data to be removed from the cache and the inaccurately prefetched data is not accessed, which reduces performance. Additionally, even if performance is not adversely affected or improved by a small amount, excess power consumed by the processor to perform the prefetching might not be justified. Particularly, in portable devices in which the available energy is limited (e.g. from a battery), the excess power consumption can reduce battery life.